Xilinx Vivado Design Suite 2022.2

What's New in 2022.2 Key Highlights

Introducing Power Design Manager for Versal® ACAP & Kria™ SOM

Intelligent Design Run now supported for Versal devices shows average 5% QoR improvement over explore strategy *

1.4X compile time speed-up for UltraScale+™ architecture designs with Incremental Compile Flow **

Abstract Shell for DFX now supported for Versal devices and in project mode

DFX support enabled for Versal Premium SSI devices

Vivado ML What's New by Category

Expand the sections below to learn more about the new features and enhancements in Vivado® ML 2022.2.

 

Device Support

Devices enabled in the Enterprise Edition of Vivado ML 

Versal® Premium Series: XCVP1702, XCVP1802, XCVP1102

Devices enabled in Standard and Enterprise Editions 

Kria™ SOM: XCK24

Devices that are production-ready

Versal Premium Series: XCVP1202

Versal Prime Series: XCVM1502

Versal AI Core Series: XCVC1702, XCVC1502

Install and Licensing

25% reduction in peak disk footprint installation

IP Enhancements

​Infrastructure and Embedded​

 

Soft Endpoint Protection Unit (EPU) IP for protecting AXI agents residing in the PL​

Storage​

 

Embedded RDMA enabled NIC (ERNIC) now supports up to 2k Queue Pairs (QP)

Gigabit Transceiver (GT) Wizard

 

Versal GTMs now support rate switching between half and full density 

16 configurations for Versal GTY/GTYP (limited to internal BRAM capacity)

Wired​

 

100G Multi-rate Ethernet MAC Subsystems (MRMAC) 

Enabled 100G Ethernet 106G serial lane support

600G Multi-rate Ethernet MAC Subsystem (DCMAC) 

Enabled 100GE, 200GE, 400GE 106G serial per lane support 

Aurora 64B/66B 

Added support for 16 lanes of GTYP or Gigabit Transceiver Module (GTM) on Versal Premium 

Wireless​

 

Zynq® RFSoC DFE IP Update: Channel Filter and DUC-DDC UL/DL sharing 

Zynq® RFSoC DFE DPD Update: PL resource reduction 

Zynq® RFSoC DFE O-RU TRD: Updated w/ Low PHY processing only

PCIe® Subsystems 

 

CPM5 x86 host drivers for Linux and DPDK in public release on GitHub 

Versal CPM5 PCIe BMD Simulation Design (from CED Store) 

Versal CPM Tandem PCIe Design (from CED Store) 

QDMA v5.0 improved performance/resource utilization 

Multimedia 

 

Versal AI Edge enablement of soft IPs and Video Decoder Unit (VDU)

Warp Processor IP in production

Ultra HD 8K multimedia solution enablement for 

HDMI2.1

Video Mixer IP 

IP Integrator

AXI streaming NoC MxN support in IP Integrator 

New address remap feature

Vivado for default syntax checking

Address path visualization

XML to JSON format for XCI files

Simulation

Support for System Verilog “Interface Class”

Debug support for reference type System Verilog objects via tcl command and object window

VHDL-2008 support

Hardware Debug

Support for PCIe Debugger on new Versal architectures

VP1502

VP1702

VP1802

HBM2E Debugger support on Versal HBM devices

Integrated Bit Error Ratio Tester (IBERT) support on new Versal architectures

VP1502

VP1702

VP1802

Implementation

QoR optimization for high fanout nets  

Placer replication for hard IP blocks 

Two new partitioning constraints for SSI designs  

LUT decomposition option to reduce congestion 

Incremental implementation enabled for monolithic Versal devices 

Support ECO flow for Versal devices 

Timing Closure

New content added to QoR assessment report

Average 5% QoR improvement for Versal designs when Intelligent Design Runs is enabled 

DFX

DFX support for SSI devices 

Abstract Shell support for Versal Premium and Versal HBM devices 

Abstract Shell support for project-based mode